1. Field of Technology
The present invention relates to a low-pass filter formed of a switched capacitor circuit, and to a semiconductor pressure sensor apparatus which utilizes such a low-pass filter.
2. Description of Prior Art
Due to their advantages of being small in size and having high performance, various types of semiconductor pressure sensor apparatus are utilized in applications such as for pressure detection within the air intake pipes or exhaust pipes of vehicle engines, or in non-vehicle applications such as in gas meters, etc. Since a semiconductor pressure sensor has excellent response characteristics, they are suitable for use in detecting rapid changes in pressure. However, the high speed of response of a semiconductor pressure sensor is a disadvantage in applications in which it is required to detect average changes in pressure, with high-frequency components of the pressure changes being excluded. In such a case, in which it is required to extract low-frequency components of the pressure changes, it is necessary to use a low-pass filter to remove the high-frequency components from a detection signal that is obtained from a semiconductor pressure sensor.
FIG. 7 is a circuit diagram of an example of a prior art type of semiconductor pressure sensor apparatus. With this apparatus, a detection signal that is generated by a semiconductor pressure sensor 1 is amplified by a differential amplifier 2, and the resultant output signal is transferred through a low-pass filter 3, to thereby obtain an output signal voltage that contains only low-frequency components of the pressure changes that are detected by the semiconductor pressure sensor 1.
The semiconductor pressure sensor 1 can for example be formed of a diaphragm constituted by a plate of silicon having a region that is made relatively thin, with piezoresistive elements G1˜G4 (i.e., elements which exhibit a change in resistance when subjected to distortion) formed on a surface of the diaphragm. When pressure is applied to the diaphragm, causing shape distortion to occur, the respective resistance values of the piezoresistive elements G1˜G4 are altered. The piezoresistive elements G1˜G4 are connected in a bridge configuration, so that when pressure is applied to the diaphragm then for example a potential Vp1 that appears between the mutual connection points of the piezoresistive elements G2 and G3 may be increased, while a potential Vp2 that appears between the mutual connection points of the piezoresistive elements G1 and G4 may be decreased.
The potentials Vp1, Vp2 that appear between the mutual connection points are amplified by the differential amplifier 2, to obtain an output signal having an instantaneous value of voltage designated as Vo, whose value is proportional to the voltage difference (Vp1–Vp2). Since that output signal contains high-frequency components, it is passed through the low-pass filter 3 to obtain an output signal that contains only low-frequency components, and whose instantaneous voltage value is designated as Vout.
In the following it will be assumed that switches which perform capacitor switching are implemented as FETs (field effect transistors), each controlled by a control voltage signal applied to a gate electrode, and with the ON/OFF conditions of the switch corresponding to conducting/non-conducting conditions, respectively, between the drain and source electrodes of the FET.
Usually, the low-pass filter 3 is configured as a switched capacitor circuit that is formed in an integrated circuit. The capacitor switching is performed by switches S11, S12, S13, S24, S25, S26 which are respective analog switches (where the term “analog switch” is used herein to signify a switching element constituted by a semiconductor switch device such as a MOS FET) controlled by control signals that are constituted by first and second clock signals φ1, φ2 shown in the timing diagram of FIG. 8, and are generated by a clock pulse signal generating circuit 30. FIG. 8 illustrates the phase relationships of the two-phase clock signals φ1, φ2 when each of these has a frequency of 150 kHz. Each of the set of switches S11, S12, S13 is set in the ON (i.e., conducting) state when the first clock signal φ1 is at the active level (assumed to be the high level, in the example of FIG. 8), while each of the set of switches S24, S25, S26 is set in the conducting state when the second signal φ2 is at the active level.
When the analog switches S11˜S13 and S24˜S26 are controlled as described above by the two-phase clock signals φ1, φ2 with the timing relationships shown in FIG. 8, the equivalent circuit of the operation becomes as shown in FIG. 6, i.e., with the circuit functioning as a low-pass filter. The values of the resistors R1, R2 and the cut-off frequency fc of that equivalent circuit are obtained (designating the frequency of each of the two-phase clock signals φ1, φ2 as fs, the respective capacitance values of the capacitors C1, C2 C3 as c1, c2, c3 and the resistance value of the resistors R1, R2 as r1, r2 respectively) from the following equations:r1=1/(fs. c1)  (1)r2=1/(fs. c2)  (2)fc=1/(2π. r2. c3)=fs. c2/(2π. c3)  (3)
With a usual type of semiconductor pressure sensor apparatus, the cut-off frequency fc is generally required to be approximately 100˜400 Hz. If for example the cut-off frequency is 100 Hz, then the values c2=0.25 pf, c3=60 pf, fs=150 kHz, can be used. Such capacitance and frequency values can readily be obtained by using devices that are formed in an integrated circuit.
However considering the case in which a substantially lower value of cut-off frequency is required, e.g., 1 Hz, then if the values for the frequency fs of the two-phase clock signals φ1, φ2 and for the capacitor C2 are made the same as in the above numeric example, the value of capacitor C3 must be multiplied by 100, i.e., to be made 6,000 pf. In practice, it is not possible to realize such a large value of capacitance by a capacitor that is formed in a semiconductor integrated circuit.
Thus, since it would not be practicable to substantially reduce the value of capacitor C2 below approximately 0.25 pf, it would be necessary to lower the frequency fs of the two-phase clock signals φ1, φ2 by a factor of 1:100, i.e., to approximately 1.5 kHz, in order to achieve a value of cut-off frequency as low as 1 Hz with such a prior art type of low-pass filter.
The phase relationship between the two-phase clock signals φ1, φ2 during one clock period, in the case of a prior art type of apparatus in which the frequency of each of the two-phase clock signals φ1, φ2 is 150 kHz will be considered referring again to the timing diagram of FIG. 8, and to FIGS. 5A to 5D. FIGS. 5A to 5D respectively illustrate successive conditions attained by the low-pass filter 3 (when formed as the switched capacitor circuit shown in FIG. 7) during four successive time intervals within a clock period, designated as Phase 1, Phase 2, Phase 3 and Phase 4.
Firstly as shown in FIG. 5A, during Phase 1, the capacitor C1 becomes charged to the input voltage Vo, while conversely the capacitor C2 is discharged, to reach a charge of zero. The charge in the capacitor C3 is left unchanged.
Next, considering Phase 2, as shown in FIG. 5B all of the switches S11, S12, S13, S24, S25, S26 are in the OFF (i.e., open) state, so that the charge in each of the capacitors C1, C2, C3 is left unchanged. Thus, during Phase 2, the respective voltages developed across the capacitors are left unchanged from those which existed at the end of Phase 1.
Next, considering Phase 3, as shown in FIG. 5C the capacitors C2 and C3 become connected in parallel, and the capacitor C1 becomes connected between the inverting input terminal and the non-inverting input terminal of the operational amplifier OP1. Since the inverting input terminal and the non-inverting input terminal of the operational amplifier OP1 are held at the same potential the capacitor C1 becomes discharged. The resultant discharge current flow acts to charge each of the capacitors C2 , C3 . The capacitor C2 becomes finally charged to the output signal voltage Vout that is being produced from the operational amplifier OP1 at that point in time. The amount of charging current which flows into the capacitor C3 is equal to the amount of discharge current which flows from the capacitor C1, with the charge voltage of the capacitor C3 changing accordingly. Since the voltage to which the capacitor C3 becomes charged is necessarily identical to the output voltage Vout from the operational amplifier OP1, the amount of change of that output voltage Vout is equal to the amount of change in the voltage to which the capacitor C3 is charged.
Next, considering Phase 4, as shown in FIG. 5D all of the switches S11, S12, S13, S24, S25, S26 are in the OFF state, in the same way as for the condition during Phase 3. Thus, each of the capacitors C1, C2 , C3 is left in the same condition of charge as that which existed at the end of Phase 3.
However a problem arises with respect to a change in the charge voltages of the capacitors C1, C2 during the Phase 2 interval. Immediately after the start of Phase 2, the amount of charge in the capacitor C1 is Vo.C1, while amount of charge in the capacitor C2 is zero. Since the amount of area that is available on the substrate of a semiconductor integrated circuit is extremely small, each capacitor can only have a maximum value that is very small. In addition as can be understood from equation (3) above, the value of capacitor c2 should be as small as possible, to achieve a low value of cut-off frequency for the low-pass filter, e.g., 0.25 pF. When the amount of capacitance is extremely small, then when analog switches that are respectively connected between the terminals of a capacitor and ground potential are set in the OFF state, even a tiny amount of leakage current that flows in these analog switches will have a substantial effect upon the voltage to which the capacitor is charged.
The term “leakage current” is used here to refer to a total amount of leakage current flow, which is determined by such factors as the finite amount of resistance that exists between the drain and source electrodes of a FET constituting an analog switch, when in the OFF state, and also by the leakage current that flows in the PN junction that exists between the region below the drain and source electrodes and the substrate, etc. The leakage current magnitude increases in accordance with increases in operating temperature. Referring again to the timing diagram of FIG. 8, since the cut-off frequency fc is 100 Hz, and the duration of a Phase 2 interval is 1.7 microseconds and so is extremely short, the effects of leakage current during that interval can in practice be ignored. However if the capacitor values were to be left unchanged, and the cut-off frequency fc were to be lowered to 1 Hz, then it would be necessary to lower the frequency fs of the two-phase clock signals φ1, φ2 to become 1.5 kHz as described above. If that is done, then the duration of a Phase 2 interval becomes multiplied by a factor of 100, i.e., to become 170 microseconds. In that case, with all of the switches S11, S12, S13, S24, S25, S26 in the OFF state during such a long-duration Phase 2 interval, the amount of charge in the capacitors C1, C2 will change substantially during that interval, due to leakage current flow in the switches that are connected on each side of each of these capacitors.
As a result the problem arises that an error will arise in the gain of the low-pass filter 3 in the low-frequency range and in the actual cut-off frequency of the low-pass filter (i.e., by comparison with the cut-off frequency that is derived from equation (3)).